1. Field
Embodiments discussed herein relate to a receiver circuit.
2. Description of Related Art
High-speed interface receiver circuits having analog-to-digital converters arranged at input stages recover data by a digital signal process. The circuits arranged at the input stages of the receiver circuits may perform time interleave to increase the operating margins of the circuits without changing the effective operating frequencies. For example, the frequency of clock signals is halved, two circuits are provided at the input stage of a receiver circuit, and the two circuits operate at rising edges and falling edges of the clock signals.
Related art is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2002-100988 and Japanese Unexamined Patent Application Publication No. 2005-348156.